Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

21.4.5.1.1. Calculating High and Low Counts

The calculations below show an example of how to calculate SCL high and low counts for each speed mode in the I2C controller.

The equation to calculate the proper number of l4_sp_clk clock pulses required for setting the proper SCL clocks high and low times is as follows: †

Table 207.  Equation

IC_HCNT = ceil(MIN_SCL_HIGHtime*OSCFREQ)

IC_LCNT = ceil(MIN_SCL_LOWtime*OSCFREQ)

MIN_SCL_HIGHtime = minimum high period

MIN_SCL_HIGHtime =

4000 ns for 100 kbps

600 ns for 400 kbps

60 ns for 3.4 Mbs, bus loading = 100pF

160 ns for 3.4 Mbs, bus loading = 400pF

MIN_SCL_LOWtime = minimum low period

MIN_SCL_LOWtime =

4700 ns for 100 kbps

1300 ns for 400 kbps

120 ns for 3.4Mbs, bus loading = 100pF

320 ns for 3.4Mbs, bus loading = 400pF

OSCFREQ = l4_sp_clk clock frequency (Hz)

Calculating High and Low Counts

OSCFREQ = 100 MHz 
I2Cmode = fast, 400 kbps 
MIN_SCL_HIGHtime = 600 ns 
MIN_SCL_LOWtime = 1300 ns 

IC_HCNT = ceil(600 ns * 100 MHz) IC_HCNTSCL PERIOD = 60 
IC_LCNT = ceil(1300 ns * 100 MHz) IC_LCNTSCL PERIOD = 130 
Actual MIN_SCL_HIGHtime = 60*(1/100 MHz) = 600 ns 
Actual MIN_SCL_LOWtime = 130*(1/100 MHz) = 1300 ns † 

You may configure the SCL and SDA falling time using the parameters i2c-scl-falling-time-ns and i2c-sda-falling-time-ns respectively.