Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

5.3.2. FPGA Configuration

You can configure the FPGA using an external device or through the HPS. This section highlights configuring the FPGA through the HPS.

The FPGA CB uses the FPGA mode select (MSEL) pins to determine which configuration scheme to use. The MSEL pins must be tied to the appropriate values for the configuration scheme. The table below lists supported MSEL values when the FPGA is configured by the HPS.

Table 27.  Configuration Schemes for FPGA Configuration by the HPS

Configuration Scheme

Compression Feature

Design Security Feature

POR Delay 10

MSEL[4..0] 11

cfgwdth

cdratio

Supports Partial Reconfiguration

FPP ×16

Disabled

AES Disabled

Fast

00000

0

1

Yes

Standard

00100

0

1

Yes

Disabled

AES Enabled

Fast

00001

0

2

Yes

Standard

00101

0

2

Yes

Enabled

Optional

Fast

00010

0

4

Yes

Standard

00110

0

4

Yes

FPP ×32 13

Disabled

AES Disabled

Fast

01000

1

1

No

Standard

01100

1

1

No

Disabled

AES Enabled

Fast

01001

1

4

No

Standard

01101

1

4

No

Enabled

Optional12

Fast

01010

1

8

No

Standard

01110

1

8

No

HPS software sets the clock-to-data ratio field (cdratio) and configuration data width bit (cfgwdth) in the control register (ctrl) to match the MSEL pins. The cdratio field and cfgwdth bit must be set before the start of configuration.

The FPGA manager connects to the configuration logic in the FPGA portion of the device using a mode similar to how external logic (for example, MAX II or an intelligent host) configures the FPGA in fast passive parallel (FPP) mode. FPGA configuration through the HPS supports all the capabilities of FPP mode, including the following items:

  • FPGA configuration
  • Partial FPGA reconfiguration
  • FPGA I/O configuration, followed by PCI Express® (PCIe®) configuration of the remainder of FPGA
  • External single event upset (SEU) scrubbing
  • Decompression
  • Advanced Encryption Standard (AES) encryption
  • FPGA DCLK clock used for initialization phase clock

Configuring the FPGA portion of the SoC device comprises the following phases:

  1. Power up phase
  2. Reset phase
  3. Configuration phase
  4. Initialization phase
  5. User mode

The FPGA Manager can be configured to accept configuration data directly from the MPU or the DMA engine. Either the processor or the DMA engine moves data from memory to the FPGA Manager data image register space img_data_w. The L4 interconnect allocates a 4 KB region for image data. It is not necessary to increment the address when writing the image data because all accesses within the 4 KB image data region is transferred to the configuration logic.

10 For information about POR delay, refer to the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices.
11 Other MSEL values are allowed when the FPGA is configured from a non-HPS source. For information, refer to the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices.
12 You can select to enable or disable this feature.
13 When the FPGA is configured through the HPS, then FPPx32 is supported. Otherwise, if the FPGA is configured from a non-HPS (external) source, then FPPx32 is not supported. For more information refer to the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices.