Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

2.2.2. Cortex-A9 MPCore

The MPU subsystem provides the following functionality:

  • Arm* Cortex-A9 MPCore
    • One or two Arm* Cortex®-A9 processors
    • NEON™ single instruction, multiple data (SIMD) coprocessor and vector floating-point v3 (VFPv3) per processor
    • Snoop control unit (SCU) to ensure coherency between processors
    • Accelerator coherency port (ACP) that accepts coherency memory access requests
    • Interrupt controller
    • One general-purpose timer and one watchdog timer per processor
    • Debug and trace features
    • 32 KB instruction and 32 KB data level 1 (L1) caches per processor
    • Memory management unit (MMU) per processor
  • Arm* L2-310 level 2 (L2) cache
    • Shared 512 KB L2 cache
  • ACP ID mapper
    • Maps the 12-bit ID from the level 3 (L3) interconnect to the 3-bit ID supported by the ACP

A programmable address filter in the L2 cache controls which portions of the 32-bit physical address space can be accessed by each master.