Visible to Intel only — GUID: sfo1411572545918
Ixiasoft
Visible to Intel only — GUID: sfo1411572545918
Ixiasoft
7.2.1. Arm* JTAG-AP Signal Use in the Scan Manager
Signal |
Direction |
Implementation |
---|---|---|
SRSTCONNECTED[7:0] |
Input |
Tied to 0. The read-only SRSTCONNECTED field in the CSW register always reads as 0. |
PORTCONNECTED[7:0] |
Input |
Tied to 0x8F, which connects only ports 0-3 and 7. The read-only PORTCONNECTED field in the CSW register reads as 1 when the PORTSEL register is written with a value that enables one of the connected ports, and reads as 0 otherwise. |
PORTENABLED[7:0] |
Input |
Tied to 0x8F, so all connected ports are always considered powered on. The Arm* JTAG AP PSTA register is not supported. Software does not need to monitor the status of ports 0-3 because they are always on. For port 7, software can read the mode field of the stat register in the FPGA manager to determine the FPGA power status. |
nSRSTOUT[7:0] |
Output |
Not connected. Writing to the SRST_OUT field of the CSW register has no effect. |
nTRST*[7:0] |
Output |
nTRST*[7] is connected to the FPGA JTAG TAP controller and nTRST*[6:0] are not connected. Writing to the TRST_OUT field of the CSW register (the trst bit of the stat register in the scan manager) has an effect only when port 7 is enabled by software. For details, refer to “Communicating with the JTAG TAP Controller". |