Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

3.3.5. Safe Mode

Safe mode is enabled in the HPS by a cold reset. Also, if the ensfmdwr bit in the ctrl register is set, clock manager responds to the Safe Mode request from Reset Manager on a warm reset and sets the Safe Mode bit. No other control register bits are affected by the safe mode request from the Reset Manager.

Note: By default the preloader generated by the SoC EDS tool sets the ensfmdwr bit after bringing the clocks out from reset. In order to ensure the stability of the system, Intel recommends that you do not clear the ensfmdwr bit during any of the later HPS boot stages.

When safe mode is enabled, the main PLL hardware-managed clocks (C0-C2) are bypassed to osc1_clk clock and are directly generated from osc1_clk. While in safe mode, clock manager register settings, which control clock behavior, are not changed. However, the hardware bypasses these settings and uses safe, default settings.

The hardware-managed clocks are forced to their safe mode values such that the following conditions occur:

  • The hardware-managed clocks are bypassed to osc1_clk, including counters in the main PLL.
  • Programmable dividers select the reset default values.
  • The flash controller clocks multiplexer selects the output from the peripheral PLL.
  • All clocks are enabled.

A write by software is the only way to clear the safe mode bit (safemode) of the ctrl register.

Note: Before coming out of safe mode, all registers and clocks must be configured correctly. It is possible to program the clock manager in such a way that only a cold reset can return the clocks to a functioning state. Intel strongly recommends using provided libraries to configure and control HPS clocks.