Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

14.3. NAND Flash Controller Signal Descriptions

The HPS I/O pins support a single x8 device. The following table lists the signals:
Table 107.  NAND Flash Interface Signals

Signal

Width

I/O

Description

ad

8

in/out

Command, address and data for the flash device

ale

1

out

Address latch enable

ce_n

1

out

Output Active‑low chip enable

cle

1

out

Command latch enable

re_n

1

out

Active‑low read enable signal

rb

1

in

Ready/busy signal

we_n

1

out

Active‑low write enable signal

wp_n

1

out

Active‑low write protect signal