Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

2. Introduction to the Hard Processor System

The Cyclone® V system-on-a-chip (SoC) is composed of two distinct portions- a single- or dual-core Arm* Cortex®-A9 hard processor system (HPS) and an FPGA. The HPS architecture integrates a wide set of peripherals that reduce board size and increase performance within a system.

The SoC features the FPGA I/O, which is I/O pins dedicated to the FPGA fabric.

Figure 1.  Intel® SoC Device Block Diagram

The HPS consists of the following types of modules:

  • Microprocessor unit (MPU) subsystem with single or dual Arm* Cortex®-A9 MPCore* processors
  • Flash memory controllers
  • SDRAM controller subsystem
  • System interconnect
  • On-chip memories
  • Support peripherals
  • Interface peripherals
  • Debug components
  • Phase-locked loops (PLLs)

The HPS incorporates third-party intellectual property (IP) from several vendors.

The dual-processor HPS supports symmetric (SMP) and asymmetric (AMP) multiprocessing.

The FPGA portion of the device contains:

  • FPGA fabric
  • Control block (CB)
  • PLLs
  • High-speed serial interface (HSSI) transceivers, depending on the device variant
  • Hard PCI Express* (PCI-e) controllers
  • Hard memory controllers

The HPS and FPGA communicate with each other through bus interfaces that bridge the two distinct portions. On a power-on reset, the HPS can boot from multiple sources, including the FPGA fabric and external flash. The FPGA can be configured through the HPS or an externally supported device.

The HPS and FPGA portions of the device each have their own pins. Pins are not freely shared between the HPS and the FPGA fabric. The HPS I/O pins are configured by boot software executed by the MPU in the HPS. Software executing on the HPS accesses control registers in the system manager to assign HPS I/O pins to the available HPS modules. The FPGA I/O pins are configured by an FPGA configuration image through the HPS or any external source supported by the device.

The MPU subsystem can boot from flash devices connected to the HPS pins. When the FPGA portion is configured by an external source, the MPU subsystem can boot from flash memory devices available to the FPGA portion of the device.

The HPS and FPGA portions of the device have separate external power supplies and independently power on. You can power on the HPS without powering on the FPGA portion of the device. However, to power on the FPGA portion, the HPS must already be on or powered at the same time as the FPGA portion. You can also turn off the FPGA portion of the device while leaving the HPS power on.
Table 2.  Valid SoC Power Modes
HPS FPGA Valid?
Off Off Yes
Off On No
On Off Yes
On On Yes